Nonlinear analysis of phase-locked loops and computer architectures

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Keywords: Nonlinear analysis, phase-locked loop, PLL, clock skew, phase synchronization, clock generator

Phase-locked loops (PLLs) are widely used in telecommunication and computer architectures. They were invented in the 1930s-1940s (De Bellescize, 1932; Wendt & Fredentall, 1943) and then intensive studies of the theory and practice of PLLs were carried out (Viterbi, 1966; Lindsey, 1972; Gardner, 1979; Lindsey and Chie, 1981; Leonov et al., 1992; Encinas, 1993; Nash, 1994; Brennan, 1996; Stensby, 1997).

One of the first applications of phase-locked loop (PLL) is related to the problems of data transfer by radio signal. In radio engineering PLL is applied to a carrier synchronization, carrier recovery, demodulation, and frequency synthesis (see, e.g., (Stephens, 2002; Ugrumov, 2000)).

After the appearance of architecture with chips, operating on different frequencies, the phase-locked loops are used to generate internal frequencies of chips and synchronization of operation of different devices and data buses (Young et al., 1992; Egan, 2000; Kroupa, 2003; Razavi, 2003; Shu & Sanchez-Sinencio, 2005; Manassewitsch, 2005). For example, the modern computer motherboards contain different devices and data buses operating on different frequencies, which are often in the need for synchronization (Wainner & Richmond, 2003; Buchanan & Wilson, 2001).

Another actual application of PLL is the problem of saving energy. One of the solutions of this problem for processors is a decreasing of kernel frequency with processor load. The independent phase-locked loops permit one to distribute more uniformly a kernel load to save the energy and to diminish a heat generation on account of that each kernel operates on its own frequency. Now the phase-locked loops are widely used for the solution of the problems of clock skew and synchronization for the sets of chips of computer architectures and chip microarchitecture. For example, a clock skew is very important characteristic of processors (see, e.g., (Xanthopoulos, 2001; Bindal, 2003)).

Various methods for analysis of phase-locked loops are well developed by engineers and are considered in many publications (see, e.g., (Banerjee, 2006; Best, 2003; Kroupa, 2003; Bianchi, 2005; Egan, 2007)), but the problems of construction of adequate nonlinear models and nonlinear analysis of such models are still far from being resolved and require using special methods of qualitative theory of differential, difference, integral, and integro-differential equations (Gelig et al., 1978; Leonov et al., 1996a; Leonov et al., 1996b; Leonov & Smirnova, 2000; Abramovitch, 2002; Suarez & Quere, 2003; Margaris, 2004; Kudrewicz & Wasowicz, 2007; Kuznetsov, 2008; Leonov, 2006).

Publications

1. G.A. Leonov, N.V. Kuznetsov, S.M. Seledzhi, Nonlinear Analysis and Design of Phase-Locked Loops, (book chapter in "Automation control – Theory and Practice", A.D. Rodić (Ed.), In-Tech, 2009), pp. 89-114 (ISBN 978-953-307-039-1)
2. Kuznetsov N.V., Stability and Oscillations of Dynamical Systems: Theory and Applications. Jyväskylä University Printing House, 2008 (ISBN: 978-951-39-3428-6)
3. E.V. Kudryashova, N.V. Kuznetsov, G.A. Leonov, P. Neittaanmaki, S.M. Seledzhi, Analysis and synthesis of clock generator, International conference on Physics and Control, Book of selected papers, World Scientific, 2010.
4. N.V. Kuznetsov, G.A. Leonov, P. Neittaanmäki S.M. Seledzhi, Analysis and design of computer architecture circuits with controllable delay line, International Conference on Informatics in Control, Automation and Robotics, Proceedings, Vol. 3 – Signal processing, Systems Modeling and Control, 2009, pp. 222-224 (ISBN: 978-989-674-001-6)
5. N.V. Kuznetsov, G.A. Leonov, and S.M. Seledzhi, Nonlinear analysis of the Costas loop and phase-locked loop with squarer, Eleventh IASTED International Conference on Signal and Image Processing, Proceedings, 2009, pp. 1-7 (ISBN: 978-0-88986-803-8)
6. Leonov, G.A. & Seledghi, S.M. (2005a). Stability and bifurcations of phase-locked loops for digital signal processors, International journal of bifurcation and chaos, 15(4), pp. 1347–1360
7. Leonov, G.A. & Seledghi, S.M. (2005). Design of phase-locked loops for digital signal processors, International Journal of Innovative Computing, Information Control, 1(4), pp. 779–789
8. Leonov, G.A. (2006). Phase-Locked Loops. Theory and Application, Automation and remote control, 10, pp. 47–55

Main references

• Abramovitch, D. (2002). Phase-Locked Loops: A control Centric Tutorial, Proceedings of the American Control Conference 2002. vol. 1, pp. 1–15
• Banerjee, D. (2006). Pll Performance, Simulation and Design, Ed. 4. Dog Ear Publishing
• De Bellescize, H. (1932). La Reseption synchrone, Onde Electrique
• Best Ronald, E. (2003). Phase-Lock Loops: Design, Simulation and Application 5ed, McGraw Hill
• Bianchi, G. (2005). Phase-locked Loop Synthesizer Simulation, McGraw-Hill
• Bindal, N., Kelly, T., Velastegui, N. & Wong, K.L. (2003). Scalable sub-10ps Skew Global Clock Distribution for a 90nm Multi-GHz IA Microprocessor, Proceedings of IEEE International Solid-State Circuits Conference, Digest of Technical Papers. ISSCC. vol. 1, pp. 346–498
• Brennan, P.V. (1996). Phase-locked loops: principles and practice, Macmillan Press
• Buchanan, W. & Wilson, A. (2001). Advanced PC architecture, Addison-Wesley
• Chen, Wai-Kai. (2003). The circuits and filters handbook, CRC Press
• Gardner, F. (1979). Phase–lock techniques, 2ed, John Wiley & Sons
• Giannini, F. & Leuzzi, G. (2004). Nonlinear microwave circuit design, John Wiley & Sons
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• with Nonunique Equilibrium State, Nauka, Moscow (in Russian)
• Goldman, S.J. (2007). Phase-locked Loop Engineering Handbook for Integrated Circuits, Artech House
• Egan, W. (2007). Phase-Lock Basics, Wiley-IEEE
• Egan, W. (2000). Frequency Synthesis by Phase Lock, 2nd ed., John Wiley & Sons
• Encinas, J. (1993). Phase Locked Loops, Springer
• Kroupa, V. (2003). Phase Lock Loops and Frequency Synthesis, John Wiley & Sons
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