Nonlinear analysis of phase-locked loops and computer architectures

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Keywords: Nonlinear analysis, phase-locked loop, PLL, clock skew, phase synchronization, clock generator

Phase-locked loops (PLLs) are widely used in telecommunication and computer architectures. They were invented in the 1930s-1940s (De Bellescize, 1932; Wendt & Fredentall, 1943) and then intensive studies of the theory and practice of PLLs were carried out (Viterbi, 1966; Lindsey, 1972; Gardner, 1979; Lindsey and Chie, 1981; Leonov et al., 1992; Encinas, 1993; Nash, 1994; Brennan, 1996; Stensby, 1997).

One of the first applications of phase-locked loop (PLL) is related to the problems of data transfer by radio signal. In radio engineering PLL is applied to a carrier synchronization, carrier recovery, demodulation, and frequency synthesis (see, e.g., (Stephens, 2002; Ugrumov, 2000)).

After the appearance of architecture with chips, operating on different frequencies, the phase-locked loops are used to generate internal frequencies of chips and synchronization of operation of different devices and data buses (Young et al., 1992; Egan, 2000; Kroupa, 2003; Razavi, 2003; Shu & Sanchez-Sinencio, 2005; Manassewitsch, 2005). For example, the modern computer motherboards contain different devices and data buses operating on different frequencies, which are often in the need for synchronization (Wainner & Richmond, 2003; Buchanan & Wilson, 2001).

Another actual application of PLL is the problem of saving energy. One of the solutions of this problem for processors is a decreasing of kernel frequency with processor load. The independent phase-locked loops permit one to distribute more uniformly a kernel load to save the energy and to diminish a heat generation on account of that each kernel operates on its own frequency. Now the phase-locked loops are widely used for the solution of the problems of clock skew and synchronization for the sets of chips of computer architectures and chip microarchitecture. For example, a clock skew is very important characteristic of processors (see, e.g., (Xanthopoulos, 2001; Bindal, 2003)).

Various methods for analysis of phase-locked loops are well developed by engineers and are considered in many publications (see, e.g., (Banerjee, 2006; Best, 2003; Kroupa, 2003; Bianchi, 2005; Egan, 2007)), but the problems of construction of adequate nonlinear models and nonlinear analysis of such models are still far from being resolved and require using special methods of qualitative theory of differential, difference, integral, and integro-differential equations (Gelig et al., 1978; Leonov et al., 1996a; Leonov et al., 1996b; Leonov & Smirnova, 2000; Abramovitch, 2002; Suarez & Quere, 2003; Margaris, 2004; Kudrewicz & Wasowicz, 2007; Kuznetsov, 2008; Leonov, 2006).

Publications

1. Leonov G.A., Kuznetsov N.V., Yuldashev M.V., Yuldashev R.V., Analytical method for computation of phase-detector characteristic, IEEE Transactions on Circuits and Systems Part II, vol. 59, num. 10, 2012, pp. 633-637 [DOI]
2. G.A. Leonov, N.V. Kuznetsov, M.V. Yuldashev, R.V. Yuldashev, Differential equations of Costas loop, Doklady Mathematics, 86(2), 2012, pp. 723–728 [DOI]
3. G.A. Leonov, N.V. Kuznetsov, M.V. Yuldashev, R.V. Yuldashev, Computation of Phase Detector Characteristics in Synchronization Systems, Doklady Mathematics, 2011, Vol. 84, No. 1, pp. 586-590 [DOI]
4. N.V. Kuznetsov, G.A. Leonov, M.V. Yuldashev, R.V. Yuldashev, Analytical methods for computation of phase-detector characteristics and PLL design, ISSCS 2011 – IEEE International Symposium on Signals, Circuits and Systems, Proceedings, 2011, Art. num. 5978639, pp.7-10 [DOI]
5. N.V. Kuznetsov, G.A. Leonov, P. Neittaanmäki, S.M. Seledzhi, M.V. Yuldashev, R.V. Yuldashev, High-frequency analysis of phase-locked loop and phase detector characteristic computation, ICINCO 2011 - Proceedings of the 8th International Conference on Informatics in Control, Automation and Robotics, Volume 1, 2011, pp.272-278 (doi: 10.5220/0003522502720278)
6. G.A. Leonov, S.M. Seledzhi, N.V. Kuznetsov, P. Neittaanmäki, Asymptotic analysis of phase control system for clocks in multiprocessor arrays, ICINCO 2010 - Proceedings of the 7th International Conference on Informatics in Control, Automation and Robotics, Vol. 3, 2010, pp. 99-102 [DOI]
7. N.V. Kuznetsov, G.A. Leonov, P. Neittaanmäki S.M. Seledzhi, Analysis and design of computer architecture circuits with controllable delay line, ICINCO 2009 - 6th International Conference on Informatics in Control, Automation and Robotics, Proceedings, Vol. 3 SPSMC, 2009, pp. 221-224 [DOI]
8. N.V. Kuznetsov, G.A. Leonov, and S.M. Seledzhi, Nonlinear analysis of the Costas loop and phase-locked loop with squarer, Proceedings of Eleventh IASTED International Conference Signal and Image Processing, Vol. 654, 2009, pp. 1-7 (ACTA Press)
9. Kuznetsov N., Leonov G., Seledzhi S., Phase Locked Loops Design And Analysis, ICINCO 2008 - 5th International Conference on Informatics in Control, Automation and Robotics, Proceedings Volume SPSMC, 2008, pp. 114-118 [DOI]
10. G.A. Leonov, N.V. Kuznetsov, S.M. Seledzhi, Nonlinear Analysis and Design of Phase-Locked Loops, (book chapter in "Automation control – Theory and Practice", A.D. Rodić (Ed.), In-Tech, 2009), pp. 89-114 (ISBN 978-953-307-039-1)
11. Kuznetsov N.V., Stability and Oscillations of Dynamical Systems: Theory and Applications. Jyväskylä University Printing House, 2008 (ISBN: 978-951-39-3428-6)
12. E.V. Kudryashova, N.V. Kuznetsov, G.A. Leonov, P. Neittaanmaki, S.M. Seledzhi, Analysis and synthesis of clock generator, International conference on Physics and Control, Book of selected papers, World Scientific, 2010.
13. N.V. Kuznetsov, G.A. Leonov, P. Neittaanmäki S.M. Seledzhi, Analysis and design of computer architecture circuits with controllable delay line, International Conference on Informatics in Control, Automation and Robotics, Proceedings, Vol. 3 – Signal processing, Systems Modeling and Control, 2009, pp. 222-224 (ISBN: 978-989-674-001-6)
14. N.V. Kuznetsov, G.A. Leonov, and S.M. Seledzhi, Nonlinear analysis of the Costas loop and phase-locked loop with squarer, Eleventh IASTED International Conference on Signal and Image Processing, Proceedings, 2009, pp. 1-7 (ISBN: 978-0-88986-803-8)

Main references

• Abramovitch, D. (2002). Phase-Locked Loops: A control Centric Tutorial, Proceedings of the American Control Conference 2002. vol. 1, pp. 1–15
• Banerjee, D. (2006). Pll Performance, Simulation and Design, Ed. 4. Dog Ear Publishing
• De Bellescize, H. (1932). La Reseption synchrone, Onde Electrique
• Best Ronald, E. (2003). Phase-Lock Loops: Design, Simulation and Application 5ed, McGraw Hill
• Bianchi, G. (2005). Phase-locked Loop Synthesizer Simulation, McGraw-Hill
• Bindal, N., Kelly, T., Velastegui, N. & Wong, K.L. (2003). Scalable sub-10ps Skew Global Clock Distribution for a 90nm Multi-GHz IA Microprocessor, Proceedings of IEEE International Solid-State Circuits Conference, Digest of Technical Papers. ISSCC. vol. 1, pp. 346–498
• Brennan, P.V. (1996). Phase-locked loops: principles and practice, Macmillan Press
• Buchanan, W. & Wilson, A. (2001). Advanced PC architecture, Addison-Wesley
• Chen, Wai-Kai. (2003). The circuits and filters handbook, CRC Press
• Gardner, F. (1979). Phase–lock techniques, 2ed, John Wiley & Sons
• Giannini, F. & Leuzzi, G. (2004). Nonlinear microwave circuit design, John Wiley & Sons
• Gelig, A.Kh., Leonov, G.A. & and Yakubovich, V.A. (1978). Stability of Nonlinear Systems
• with Nonunique Equilibrium State, Nauka, Moscow (in Russian)
• Goldman, S.J. (2007). Phase-locked Loop Engineering Handbook for Integrated Circuits, Artech House
• Egan, W. (2007). Phase-Lock Basics, Wiley-IEEE
• Egan, W. (2000). Frequency Synthesis by Phase Lock, 2nd ed., John Wiley & Sons
• Encinas, J. (1993). Phase Locked Loops, Springer
• Kroupa, V. (2003). Phase Lock Loops and Frequency Synthesis, John Wiley & Sons
• Kudrewicz, J. & Wasowicz S. (2007). Equations of Phase-Locked Loops: Dynamics on the Circle, Torus and Cylinder, World Scientific
• Kung, S. (1988). VLSI Array Processors, Prentice Hall
• Lapsley, P., Bier, J., Shoham, A. & Lee, E. (1997).DSP Processor Fundamentals Architecture and Features, IEE Press
• Lindsey, W. (1972). Sinchronization systems in communication and control, Prentice-Hall
• Leonov, G., Reitmann, V. & Smirnova, V. (1992). Nonlocal Methods for Pendulum-LikeFeedback Systems, Teubner Verlagsgesselschaft, Stuttgart–Leipzig
• Leonov, G., Ponomarenko, D. & Smirnova, V. (1996a). Frequency-Domain Methods for Nonlinear Analysis. Theory and Applications, World Scientific
• Leonov, G.A., Burkin, I.M. & Shepeljavy, A.I. (1996b). Frequency Methods in Oscillation
• Theory, Kluver, Dordrecht
• Leonov, G.A. & Smirnova, V.B. (2000). Mathematical Problems of the Phase Synchronization Theory, Nauka, St. Petersburg
• Leonov, G.A. (2001). Mathematical Problems of Control Theory, World Scientific
• Leonov, G. A. & Seledzhi, S.M. (2002). Phase-locked loops in array processors, Nevsky dialekt, St.Petersburg (in Russian)
• Lindsey, W. & Chie, C. (1981). A Survey of Digital Phase Locked Loops. Proceedings of the IEEE, vol. 69, pp. 410–431
• Manassewitsch, Vadim. (2005). Frequency synthesizers: theory and design, Wiley
• Margaris, N.I. (2004). Theory of the Non-Linear Analog Phase Locked Loop, Springer Verlag
• Nash, G. (1994). Phase Locked Loop, Design Fundamentals, Motorola, Phoenix
• Noldus, E., (1977). New Direct Lyapunov-type Method for Studying Synchronization Problems, Automatika, 1977, vol. 13, no. 2, pp. 139–151
• Osborne, H.C. (1980). Stability Analysis of an N-th Power Digital Phase Locked Loop. Part. I: First-order DPLL, IEEE Trans. Commun., vol. 28, pp. 1343–1354
• Razavi, B. (2003). Phase-Locking in High-Performance Systems: From Devices to Architectures, John Wiley & Sons
• Razavi, B. (2001). Design of Analog CMOS Integrated Circuits, McGraw Hill Saint-Laurent, M., Swaminathan, M. & Meindl, J.D. (2001). On the Micro-Architectural Impact of Clock Distribution Using Multiple PLLs, In Proceedings of International Conference on Computer Design, pp. 214–220
• Shakhgildyan, V.V. & Lyakhovkin, A.A. (1972). Sistemy fazovoi avtopodstroiki chastity (Phase Locked Loops), Svyaz, Moscow (in Russian)
• Shu, K. & Sanchez-Sinencio, E. (2005). CMOS PLL Synthesizers: Analysis and Design, Springer
• Simpson, R. (1994). Digital Signal Processing Using The Motorola DSP Family, Prentice Hall
• Smith, S.W. (1999). The Scientist and Engineers Guide to Digital Signal Processing, California Technical Publishing, San Diego
• Solonina, A., Ulakhovich, D. & Yakovlev, L. (2001). Algorithms and Processors for Digital Signal Processing, BHV, St. Petersburg (in Russian)
• Solonina, A., Ulahovich, D. & Jakovlev, L. (2000). The Motorola Digital Signal Processors, BHV, St. Petersburg (in Russian)
• Stensby, J.L. (1997). Phase-locked Loops: Theory and Applications. CRC Press
• Stephens, D.R. (2002). Phase-Locked Loops For Wireless Communications (Digital, Analog and Optical Implementations), Second Edition, Kluwer Academic Publishers
• Suarez, A. & Quere, R. (2003). Stability Analysis of Nonlinear Microwave Circuits, Artech House
• Ugrumov, E. (2000). Digital engineering, BHV, St.Petersburg (in Russian)
• Viterbi, A. (1966). Principles of coherent communications, McGraw-Hill
• Wainner, S. & Richmond, R. (2003). The book of overclocking: tweak your PC to unleash its power. No Starch Press
• Wendt, K. & Fredentall, G. (1943). Automatic frequency and phase control of synchronization in TV receivers, Proc. IRE, vol. 31, no. 1, pp. 1–15
• Wolaver, D.H. (1991). Phase-locked Loop Circuit Design, Prentice Hall
• Xanthopoulos, T., et al. (2001). The Design and Analysis of the Clock. Distribution. Network for a 1.2GHz Alpha Microprocessor, IEEE ISSCC Tech. Dig., pp. 232–233
• Yakubovich, V., Leonov, G. & Gelig, A. (2004). Stability of Systems with Discontinuous Nonlinearities, World Scientisic
• Young, I.A., Greason, J. & Wong, K. (1992). A PLL clock generator with 5 to 110MHz of lock range for microprocessors. IEEE J. Solid-State Circuits, ol. 27, no. 11, pp. 1599–1607